The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed.
For example, in IC manufacturing, testlines (or test keys) are frequently included in a semiconductor wafer, often in scribe line areas between adjacent wafer dies. Each testline typically includes a plurality of testing devices which may be similar to those used to form IC products in the wafer die area. By studying parametric test results in the testing devices, it is possible to detect IC manufacturing errors and monitor the performance of various stages of the IC manufacturing process.